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2009 | Thesis | IST-REx-ID: 4363
Singh, Vasu. “Formalizing and Verifying Transactional Memories.” Formalizing and Verifying Transactional Memories, EPFL Lausanne, 2009.View
2008 | Thesis | IST-REx-ID: 4409
Prabhu, Vinayak. Games for the Verification of Timed Systems. University of California, Berkeley, 2008, pp. 1–137.View
2008 | Thesis | IST-REx-ID: 4415
Matic, Slobodan. Compositionality in Deterministic Real-Time Embedded Systems. University of California, Berkeley, 2008, pp. 1–148.View