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2021 | Conference Paper | IST-REx-ID: 10002 |
Chatterjee, Krishnendu, et al. “Symbolic Time and Space Tradeoffs for Probabilistic Verification.” Proceedings of the 36th Annual ACM/IEEE Symposium on Logic in Computer Science, Institute of Electrical and Electronics Engineers, 2021, pp. 1–13, doi:10.1109/LICS52264.2021.9470739.View | DOI | Download Preprint (ext.) | arXiv