Inherent limitations of hybrid transactional memory

D.-A. Alistarh, J. Kopinsky, P. Kuznetsov, S. Ravi, N. Shavit, in:, Springer, 2015, pp. 185–199.


Conference Paper | Published | English
Author
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Series Title
LNCS
Abstract
Several Hybrid Transactional Memory (HyTM) schemes have recently been proposed to complement the fast, but best-effort nature of Hardware Transactional Memory (HTM) with a slow, reliable software backup. However, the costs of providing concurrency between hardware and software transactions in HyTM are still not well understood. In this paper, we propose a general model for HyTM implementations, which captures the ability of hardware transactions to buffer memory accesses. The model allows us to formally quantify and analyze the amount of overhead (instrumentation) caused by the potential presence of software transactions.We prove that (1) it is impossible to build a strictly serializable HyTM implementation that has both uninstrumented reads and writes, even for very weak progress guarantees, and (2) the instrumentation cost incurred by a hardware transaction in any progressive opaque HyTM is linear in the size of the transaction’s data set.We further describe two implementations which exhibit optimal instrumentation costs for two different progress conditions. In sum, this paper proposes the first formal HyTM model and captures for the first time the trade-off between the degree of hardware-software TM concurrency and the amount of instrumentation overhead.
Publishing Year
Date Published
2015-01-01
Acknowledgement
P. Kuznetsov-The author is supported by the Agence Nationale de la Recherche, ANR-14-CE35-0010-01, project DISCMAT. N. Shavit-Support is gratfeully acknowledgedfrom the National Science Foundation under grants CCF-1217921, CCF-1201926, and IIS-1447786, the Department of Energy under grant ER26116/DE-SC0008923, and the Oracle and Intel corporations.
Volume
9363
Page
185 - 199
Conference
DISC: Distributed Computing
IST-REx-ID

Cite this

Alistarh D-A, Kopinsky J, Kuznetsov P, Ravi S, Shavit N. Inherent limitations of hybrid transactional memory. In: Vol 9363. Springer; 2015:185-199. doi:10.1007/978-3-662-48653-5_13
Alistarh, D.-A., Kopinsky, J., Kuznetsov, P., Ravi, S., & Shavit, N. (2015). Inherent limitations of hybrid transactional memory (Vol. 9363, pp. 185–199). Presented at the DISC: Distributed Computing, Springer. https://doi.org/10.1007/978-3-662-48653-5_13
Alistarh, Dan-Adrian, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, and Nir Shavit. “Inherent Limitations of Hybrid Transactional Memory,” 9363:185–99. Springer, 2015. https://doi.org/10.1007/978-3-662-48653-5_13.
D.-A. Alistarh, J. Kopinsky, P. Kuznetsov, S. Ravi, and N. Shavit, “Inherent limitations of hybrid transactional memory,” presented at the DISC: Distributed Computing, 2015, vol. 9363, pp. 185–199.
Alistarh D-A, Kopinsky J, Kuznetsov P, Ravi S, Shavit N. 2015. Inherent limitations of hybrid transactional memory. DISC: Distributed Computing, LNCS, vol. 9363. 185–199.
Alistarh, Dan-Adrian, et al. Inherent Limitations of Hybrid Transactional Memory. Vol. 9363, Springer, 2015, pp. 185–99, doi:10.1007/978-3-662-48653-5_13.

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