--- _id: '6428' abstract: - lang: eng text: 'Safety and security are major concerns in the development of Cyber-Physical Systems (CPS). Signal temporal logic (STL) was proposedas a language to specify and monitor the correctness of CPS relativeto formalized requirements. Incorporating STL into a developmentprocess enables designers to automatically monitor and diagnosetraces, compute robustness estimates based on requirements, andperform requirement falsification, leading to productivity gains inverification and validation activities; however, in its current formSTL is agnostic to the input/output classification of signals, andthis negatively impacts the relevance of the analysis results.In this paper we propose to make the interface explicit in theSTL language by introducing input/output signal declarations. Wethen define new measures of input vacuity and output robustnessthat better reflect the nature of the system and the specification in-tent. The resulting framework, which we call interface-aware signaltemporal logic (IA-STL), aids verification and validation activities.We demonstrate the benefits of IA-STL on several CPS analysisactivities: (1) robustness-driven sensitivity analysis, (2) falsificationand (3) fault localization. We describe an implementation of our en-hancement to STL and associated notions of robustness and vacuityin a prototype extension of Breach, a MATLAB®/Simulink®toolboxfor CPS verification and validation. We explore these methodologi-cal improvements and evaluate our results on two examples fromthe automotive domain: a benchmark powertrain control systemand a hydrogen fuel cell system.' article_processing_charge: No author: - first_name: Thomas full_name: Ferrere, Thomas id: 40960E6E-F248-11E8-B48F-1D18A9856A87 last_name: Ferrere orcid: 0000-0001-5199-3143 - first_name: Dejan full_name: Nickovic, Dejan id: 41BCEE5C-F248-11E8-B48F-1D18A9856A87 last_name: Nickovic - first_name: Alexandre full_name: Donzé, Alexandre last_name: Donzé - first_name: Hisahiro full_name: Ito, Hisahiro last_name: Ito - first_name: James full_name: Kapinski, James last_name: Kapinski citation: ama: 'Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. Interface-aware signal temporal logic. In: Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. ACM; 2019:57-66. doi:10.1145/3302504.3311800' apa: 'Ferrere, T., Nickovic, D., Donzé, A., Ito, H., & Kapinski, J. (2019). Interface-aware signal temporal logic. In Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control (pp. 57–66). Montreal, Canada: ACM. https://doi.org/10.1145/3302504.3311800' chicago: 'Ferrere, Thomas, Dejan Nickovic, Alexandre Donzé, Hisahiro Ito, and James Kapinski. “Interface-Aware Signal Temporal Logic.” In Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, 57–66. ACM, 2019. https://doi.org/10.1145/3302504.3311800.' ieee: 'T. Ferrere, D. Nickovic, A. Donzé, H. Ito, and J. Kapinski, “Interface-aware signal temporal logic,” in Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, Montreal, Canada, 2019, pp. 57–66.' ista: 'Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. 2019. Interface-aware signal temporal logic. Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. HSCC: Hybrid Systems Computation and Control, 57–66.' mla: 'Ferrere, Thomas, et al. “Interface-Aware Signal Temporal Logic.” Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, ACM, 2019, pp. 57–66, doi:10.1145/3302504.3311800.' short: 'T. Ferrere, D. Nickovic, A. Donzé, H. Ito, J. Kapinski, in:, Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, ACM, 2019, pp. 57–66.' conference: end_date: 2019-04-18 location: Montreal, Canada name: 'HSCC: Hybrid Systems Computation and Control' start_date: 2019-04-16 date_created: 2019-05-13T08:13:46Z date_published: 2019-04-16T00:00:00Z date_updated: 2023-08-25T10:19:23Z day: '16' ddc: - '000' department: - _id: ToHe doi: 10.1145/3302504.3311800 external_id: isi: - '000516713900007' file: - access_level: open_access checksum: b8e967081e051d1c55ca5d18fb187890 content_type: application/pdf creator: dernst date_created: 2020-10-08T17:25:45Z date_updated: 2020-10-08T17:25:45Z file_id: '8633' file_name: 2019_ACM_Ferrere.pdf file_size: 1055421 relation: main_file success: 1 file_date_updated: 2020-10-08T17:25:45Z has_accepted_license: '1' isi: 1 language: - iso: eng month: '04' oa: 1 oa_version: Submitted Version page: 57-66 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 25F42A32-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: Z211 name: The Wittgenstein Prize publication: 'Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control' publication_identifier: isbn: - '9781450362825' publication_status: published publisher: ACM quality_controlled: '1' scopus_import: '1' status: public title: Interface-aware signal temporal logic type: conference user_id: 4359f0d1-fa6c-11eb-b949-802e58b17ae8 year: '2019' ...