{"main_file_link":[{"open_access":"1","url":"http://openaccess.city.ac.uk/1066/"}],"volume":36,"acknowledgement":"We would like to thank Tom Giovannini from Rambus, Inc. for his detailed explana- tions of the DDR2 specification and for providing us with simulation traces. We would also like to thank Oded Maler from Verimag for discussions on the STL/PSL language and its extensions.","publication":"Formal Methods in System Design","year":"2010","page":"114 - 130","citation":{"chicago":"Jones, Kevin, Victor Konrad, and Dejan Nickovic. “Analog Property Checkers: A DDR2 Case Study.” <i>Formal Methods in System Design</i>. Springer, 2010. <a href=\"https://doi.org/10.1007/s10703-009-0085-x\">https://doi.org/10.1007/s10703-009-0085-x</a>.","short":"K. Jones, V. Konrad, D. Nickovic, Formal Methods in System Design 36 (2010) 114–130.","apa":"Jones, K., Konrad, V., &#38; Nickovic, D. (2010). Analog property checkers: a DDR2 case study. <i>Formal Methods in System Design</i>. Springer. <a href=\"https://doi.org/10.1007/s10703-009-0085-x\">https://doi.org/10.1007/s10703-009-0085-x</a>","ista":"Jones K, Konrad V, Nickovic D. 2010. Analog property checkers: a DDR2 case study. Formal Methods in System Design. 36(2), 114–130.","ama":"Jones K, Konrad V, Nickovic D. Analog property checkers: a DDR2 case study. <i>Formal Methods in System Design</i>. 2010;36(2):114-130. doi:<a href=\"https://doi.org/10.1007/s10703-009-0085-x\">10.1007/s10703-009-0085-x</a>","mla":"Jones, Kevin, et al. “Analog Property Checkers: A DDR2 Case Study.” <i>Formal Methods in System Design</i>, vol. 36, no. 2, Springer, 2010, pp. 114–30, doi:<a href=\"https://doi.org/10.1007/s10703-009-0085-x\">10.1007/s10703-009-0085-x</a>.","ieee":"K. Jones, V. Konrad, and D. Nickovic, “Analog property checkers: a DDR2 case study,” <i>Formal Methods in System Design</i>, vol. 36, no. 2. Springer, pp. 114–130, 2010."},"status":"public","type":"journal_article","publist_id":"1080","month":"06","title":"Analog property checkers: a DDR2 case study","intvolume":"        36","publisher":"Springer","doi":"10.1007/s10703-009-0085-x","author":[{"last_name":"Jones","first_name":"Kevin","full_name":"Jones, Kevin D"},{"full_name":"Konrad,Victor","first_name":"Victor","last_name":"Konrad"},{"first_name":"Dejan","full_name":"Dejan Nickovic","last_name":"Nickovic","id":"41BCEE5C-F248-11E8-B48F-1D18A9856A87"}],"publication_status":"published","day":"01","date_updated":"2021-01-12T07:56:31Z","abstract":[{"lang":"eng","text":"The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems.\n\nIn this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach.\n"}],"_id":"4379","extern":1,"quality_controlled":0,"oa":1,"issue":"2","date_created":"2018-12-11T12:08:33Z","date_published":"2010-06-01T00:00:00Z"}