Localizing faults in simulink/stateflow models with STL

E. Bartocci, T. Ferrere, N. Manjunath, D. Nickovic, in:, Association for Computing Machinery, Inc, 2018, pp. 197–206.

Download
No fulltext has been uploaded. References only!

Conference Paper | Published | English
Author
; ; ;
Department
Series Title
HSCC Proceedings
Abstract
Fault-localization is considered to be a very tedious and time-consuming activity in the design of complex Cyber-Physical Systems (CPS). This laborious task essentially requires expert knowledge of the system in order to discover the cause of the fault. In this context, we propose a new procedure that AIDS designers in debugging Simulink/Stateflow hybrid system models, guided by Signal Temporal Logic (STL) specifications. The proposed method relies on three main ingredients: (1) a monitoring and a trace diagnostics procedure that checks whether a tested behavior satisfies or violates an STL specification, localizes time segments and interfaces variables contributing to the property violations; (2) a slicing procedure that maps these observable behavior segments to the internal states and transitions of the Simulink model; and (3) a spectrum-based fault-localization method that combines the previous analysis from multiple tests to identify the internal states and/or transitions that are the most likely to explain the fault. We demonstrate the applicability of our approach on two Simulink models from the automotive and the avionics domain.
Publishing Year
Date Published
2018-04-11
Acknowledgement
This work was partially supported by the Austrian Science Fund (FWF) under grants S11402-N23 and S11405-N23 (RiSE/SHiNE), the CPS/IoT project (HRSM), the EU ICT COST Action IC1402 on Run-time Verification beyond Monitoring (ARVI), the AMASS project (ECSEL 692474), and the ENABLE-S3 project (ECSEL 692455). The CPS/IoT project receives support from the Austrian government through the Federal Ministry of Science, Research and Economy (BMWFW) in the funding program Hochschulraum-Strukturmittel (HRSM) 2016. The ECSEL Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation programme and Austria, Denmark, Germany, Finland, Czech Republic, Italy, Spain, Portugal, Poland, Ireland, Belgium, France, Netherlands, United Kingdom, Slovakia, Norway.
Page
197 - 206
Conference
HSCC: Hybrid Systems: Computation and Control
Conference Location
Porto, Portugal
Conference Date
2018-04-11 – 2018-04-13
IST-REx-ID

Cite this

Bartocci E, Ferrere T, Manjunath N, Nickovic D. Localizing faults in simulink/stateflow models with STL. In: Association for Computing Machinery, Inc; 2018:197-206. doi:10.1145/3178126.3178131
Bartocci, E., Ferrere, T., Manjunath, N., & Nickovic, D. (2018). Localizing faults in simulink/stateflow models with STL (pp. 197–206). Presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal: Association for Computing Machinery, Inc. https://doi.org/10.1145/3178126.3178131
Bartocci, Ezio, Thomas Ferrere, Niveditha Manjunath, and Dejan Nickovic. “Localizing Faults in Simulink/Stateflow Models with STL,” 197–206. Association for Computing Machinery, Inc, 2018. https://doi.org/10.1145/3178126.3178131.
E. Bartocci, T. Ferrere, N. Manjunath, and D. Nickovic, “Localizing faults in simulink/stateflow models with STL,” presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal, 2018, pp. 197–206.
Bartocci E, Ferrere T, Manjunath N, Nickovic D. 2018. Localizing faults in simulink/stateflow models with STL. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, 197–206.
Bartocci, Ezio, et al. Localizing Faults in Simulink/Stateflow Models with STL. Association for Computing Machinery, Inc, 2018, pp. 197–206, doi:10.1145/3178126.3178131.

Export

Marked Publications

Open Data IST Research Explorer

Search this title in

Google Scholar