14 Publications

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[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
Ferrere T, Henzinger TA, Kragl B. 2020. Monitoring event frequencies. 28th EACSL Annual Conference on Computer Science Logic. CSL: Computer Science Logic, LIPIcs, vol. 152.
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 7159
Ničković D, Qin X, Ferrere T, Mateis C, Deshmukh J. 2019. Shape expressions for specifying and extracting signal features. 19th International Conference on Runtime Verification. RV: Runtime Verification, LNCS, vol. 11757. 292–309.
View | DOI
 
[12]
2019 | Conference Paper | IST-REx-ID: 7232
Ferrere T, Maler O, Nickovic D. 2019. Mixed-time signal temporal logic. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). FORMATS: Formal Modeling and Anaysis of Timed Systems, LNCS, vol. 11750. 59–75.
View | DOI
 
[11]
2019 | Conference Paper | IST-REx-ID: 6428
Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. 2019. Interface-aware signal temporal logic. Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. HSCC: Hybrid Systems Computation and Control 57–66.
View | DOI
 
[10]
2019 | Journal Article | IST-REx-ID: 7109
Ferrere T, Maler O, Ničković D, Pnueli A. 2019. From real-time logic to timed automata. Journal of the ACM. 66(3), 19.
View | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 78 | OA
Bakhirkin A, Ferrere T, Nickovic D, Maler O, Asarin E. 2018. Online timed pattern matching using automata. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022. 215–232.
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
Bakhirkin A, Ferrere T, Henzinger TA, Nickovicl D. 2018. Keynote: The first-order logic of signals. 2018 International Conference on Embedded Software. EMSOFT: International Conference on Embedded Software 1–10.
View | Files available | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 299 | OA
Nickovic D, Lebeltel O, Maler O, Ferrere T, Ulus D. 2018. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. TACAS: Tools and Algorithms for the Construction and Analysis of Systems, LNCS, vol. 10806. 303–319.
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 156
Ferrere T. 2018. The compound interest in relaxing punctuality. FM: International Symposium on Formal Methods, LNCS, vol. 10951. 147–164.
View | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 182 | OA
Bakhirkin A, Ferrere T, Maler O. 2018. Efficient parametric identification for STL. Proceedings of the 21st International Conference on Hybrid Systems. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, 177–186.
View | Files available | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 183
Bartocci E, Ferrere T, Manjunath N, Nickovic D. 2018. Localizing faults in simulink/stateflow models with STL. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, 197–206.
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 81
Elgyütt A, Ferrere T, Henzinger TA. 2018. Monitoring temporal logic with clock variables. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022. 53–70.
View | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 144
Ferrere T, Henzinger TA, Saraç E. 2018. A theory of register monitors. LICS: Logic in Computer Science, ACM/IEEE Symposium on Logic in Computer Science, vol. Part F138033. 394–403.
View | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
Bakhirkin A, Ferrere T, Maler O, Ulus D. 2017. On the quantitative semantics of regular expressions over real-valued signals. FORMATS: Formal Modelling and Analysis of Timed Systems, LNCS, vol. 10419. 189–206.
View | DOI | Download Submitted Version (ext.)
 

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14 Publications

Mark all

[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
Ferrere T, Henzinger TA, Kragl B. 2020. Monitoring event frequencies. 28th EACSL Annual Conference on Computer Science Logic. CSL: Computer Science Logic, LIPIcs, vol. 152.
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 7159
Ničković D, Qin X, Ferrere T, Mateis C, Deshmukh J. 2019. Shape expressions for specifying and extracting signal features. 19th International Conference on Runtime Verification. RV: Runtime Verification, LNCS, vol. 11757. 292–309.
View | DOI
 
[12]
2019 | Conference Paper | IST-REx-ID: 7232
Ferrere T, Maler O, Nickovic D. 2019. Mixed-time signal temporal logic. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). FORMATS: Formal Modeling and Anaysis of Timed Systems, LNCS, vol. 11750. 59–75.
View | DOI
 
[11]
2019 | Conference Paper | IST-REx-ID: 6428
Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. 2019. Interface-aware signal temporal logic. Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. HSCC: Hybrid Systems Computation and Control 57–66.
View | DOI
 
[10]
2019 | Journal Article | IST-REx-ID: 7109
Ferrere T, Maler O, Ničković D, Pnueli A. 2019. From real-time logic to timed automata. Journal of the ACM. 66(3), 19.
View | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 78 | OA
Bakhirkin A, Ferrere T, Nickovic D, Maler O, Asarin E. 2018. Online timed pattern matching using automata. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022. 215–232.
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
Bakhirkin A, Ferrere T, Henzinger TA, Nickovicl D. 2018. Keynote: The first-order logic of signals. 2018 International Conference on Embedded Software. EMSOFT: International Conference on Embedded Software 1–10.
View | Files available | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 299 | OA
Nickovic D, Lebeltel O, Maler O, Ferrere T, Ulus D. 2018. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. TACAS: Tools and Algorithms for the Construction and Analysis of Systems, LNCS, vol. 10806. 303–319.
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 156
Ferrere T. 2018. The compound interest in relaxing punctuality. FM: International Symposium on Formal Methods, LNCS, vol. 10951. 147–164.
View | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 182 | OA
Bakhirkin A, Ferrere T, Maler O. 2018. Efficient parametric identification for STL. Proceedings of the 21st International Conference on Hybrid Systems. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, 177–186.
View | Files available | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 183
Bartocci E, Ferrere T, Manjunath N, Nickovic D. 2018. Localizing faults in simulink/stateflow models with STL. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, 197–206.
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 81
Elgyütt A, Ferrere T, Henzinger TA. 2018. Monitoring temporal logic with clock variables. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022. 53–70.
View | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 144
Ferrere T, Henzinger TA, Saraç E. 2018. A theory of register monitors. LICS: Logic in Computer Science, ACM/IEEE Symposium on Logic in Computer Science, vol. Part F138033. 394–403.
View | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
Bakhirkin A, Ferrere T, Maler O, Ulus D. 2017. On the quantitative semantics of regular expressions over real-valued signals. FORMATS: Formal Modelling and Analysis of Timed Systems, LNCS, vol. 10419. 189–206.
View | DOI | Download Submitted Version (ext.)
 

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