14 Publications

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[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
T. Ferrere, T. A. Henzinger, and B. Kragl, “Monitoring event frequencies,” in 28th EACSL Annual Conference on Computer Science Logic, Barcelona, Spain, 2020, vol. 152.
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 6428
T. Ferrere, D. Nickovic, A. Donzé, H. Ito, and J. Kapinski, “Interface-aware signal temporal logic,” in Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, Montreal, Canada, 2019, pp. 57–66.
View | DOI
 
[12]
2019 | Journal Article | IST-REx-ID: 7109
T. Ferrere, O. Maler, D. Ničković, and A. Pnueli, “From real-time logic to timed automata,” Journal of the ACM, vol. 66, no. 3, 2019.
View | DOI
 
[11]
2019 | Conference Paper | IST-REx-ID: 7159
D. Ničković, X. Qin, T. Ferrere, C. Mateis, and J. Deshmukh, “Shape expressions for specifying and extracting signal features,” in 19th International Conference on Runtime Verification, Porto, Portugal, 2019, vol. 11757, pp. 292–309.
View | DOI
 
[10]
2019 | Conference Paper | IST-REx-ID: 7232
T. Ferrere, O. Maler, and D. Nickovic, “Mixed-time signal temporal logic,” in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Amsterdam, The Netherlands, 2019, vol. 11750, pp. 59–75.
View | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 182 | OA
A. Bakhirkin, T. Ferrere, and O. Maler, “Efficient parametric identification for STL,” in Proceedings of the 21st International Conference on Hybrid Systems, Porto, Portugal, 2018, pp. 177–186.
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 183
E. Bartocci, T. Ferrere, N. Manjunath, and D. Nickovic, “Localizing faults in simulink/stateflow models with STL,” presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal, 2018, pp. 197–206.
View | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
A. Bakhirkin, T. Ferrere, T. A. Henzinger, and D. Nickovicl, “Keynote: The first-order logic of signals,” in 2018 International Conference on Embedded Software, Turin, Italy, 2018, pp. 1–10.
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 299 | OA
D. Nickovic, O. Lebeltel, O. Maler, T. Ferrere, and D. Ulus, “AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic,” presented at the TACAS: Tools and Algorithms for the Construction and Analysis of Systems, Thessaloniki, Greece, 2018, vol. 10806, pp. 303–319.
View | Files available | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 78 | OA
A. Bakhirkin, T. Ferrere, D. Nickovic, O. Maler, and E. Asarin, “Online timed pattern matching using automata,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Bejing, China, 2018, vol. 11022, pp. 215–232.
View | Files available | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 81
A. Elgyütt, T. Ferrere, and T. A. Henzinger, “Monitoring temporal logic with clock variables,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China, 2018, vol. 11022, pp. 53–70.
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 144
T. Ferrere, T. A. Henzinger, and E. Saraç, “A theory of register monitors,” presented at the LICS: Logic in Computer Science, Oxford, UK, 2018, vol. Part F138033, pp. 394–403.
View | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 156
T. Ferrere, “The compound interest in relaxing punctuality,” presented at the FM: International Symposium on Formal Methods, Oxford, UK, 2018, vol. 10951, pp. 147–164.
View | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
A. Bakhirkin, T. Ferrere, O. Maler, and D. Ulus, “On the quantitative semantics of regular expressions over real-valued signals,” presented at the FORMATS: Formal Modelling and Analysis of Timed Systems, Berlin, Germany, 2017, vol. 10419, pp. 189–206.
View | DOI | Download Submitted Version (ext.)
 

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14 Publications

Mark all

[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
T. Ferrere, T. A. Henzinger, and B. Kragl, “Monitoring event frequencies,” in 28th EACSL Annual Conference on Computer Science Logic, Barcelona, Spain, 2020, vol. 152.
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 6428
T. Ferrere, D. Nickovic, A. Donzé, H. Ito, and J. Kapinski, “Interface-aware signal temporal logic,” in Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, Montreal, Canada, 2019, pp. 57–66.
View | DOI
 
[12]
2019 | Journal Article | IST-REx-ID: 7109
T. Ferrere, O. Maler, D. Ničković, and A. Pnueli, “From real-time logic to timed automata,” Journal of the ACM, vol. 66, no. 3, 2019.
View | DOI
 
[11]
2019 | Conference Paper | IST-REx-ID: 7159
D. Ničković, X. Qin, T. Ferrere, C. Mateis, and J. Deshmukh, “Shape expressions for specifying and extracting signal features,” in 19th International Conference on Runtime Verification, Porto, Portugal, 2019, vol. 11757, pp. 292–309.
View | DOI
 
[10]
2019 | Conference Paper | IST-REx-ID: 7232
T. Ferrere, O. Maler, and D. Nickovic, “Mixed-time signal temporal logic,” in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Amsterdam, The Netherlands, 2019, vol. 11750, pp. 59–75.
View | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 182 | OA
A. Bakhirkin, T. Ferrere, and O. Maler, “Efficient parametric identification for STL,” in Proceedings of the 21st International Conference on Hybrid Systems, Porto, Portugal, 2018, pp. 177–186.
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 183
E. Bartocci, T. Ferrere, N. Manjunath, and D. Nickovic, “Localizing faults in simulink/stateflow models with STL,” presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal, 2018, pp. 197–206.
View | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
A. Bakhirkin, T. Ferrere, T. A. Henzinger, and D. Nickovicl, “Keynote: The first-order logic of signals,” in 2018 International Conference on Embedded Software, Turin, Italy, 2018, pp. 1–10.
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 299 | OA
D. Nickovic, O. Lebeltel, O. Maler, T. Ferrere, and D. Ulus, “AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic,” presented at the TACAS: Tools and Algorithms for the Construction and Analysis of Systems, Thessaloniki, Greece, 2018, vol. 10806, pp. 303–319.
View | Files available | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 78 | OA
A. Bakhirkin, T. Ferrere, D. Nickovic, O. Maler, and E. Asarin, “Online timed pattern matching using automata,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Bejing, China, 2018, vol. 11022, pp. 215–232.
View | Files available | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 81
A. Elgyütt, T. Ferrere, and T. A. Henzinger, “Monitoring temporal logic with clock variables,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China, 2018, vol. 11022, pp. 53–70.
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 144
T. Ferrere, T. A. Henzinger, and E. Saraç, “A theory of register monitors,” presented at the LICS: Logic in Computer Science, Oxford, UK, 2018, vol. Part F138033, pp. 394–403.
View | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 156
T. Ferrere, “The compound interest in relaxing punctuality,” presented at the FM: International Symposium on Formal Methods, Oxford, UK, 2018, vol. 10951, pp. 147–164.
View | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
A. Bakhirkin, T. Ferrere, O. Maler, and D. Ulus, “On the quantitative semantics of regular expressions over real-valued signals,” presented at the FORMATS: Formal Modelling and Analysis of Timed Systems, Berlin, Germany, 2017, vol. 10419, pp. 189–206.
View | DOI | Download Submitted Version (ext.)
 

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