14 Publications

Mark all

[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
Ferrere, T., Henzinger, T. A., & Kragl, B. (2020). Monitoring event frequencies. In 28th EACSL Annual Conference on Computer Science Logic (Vol. 152). Barcelona, Spain: Schloss Dagstuhl - Leibniz-Zentrum für Informatik. https://doi.org/10.4230/LIPIcs.CSL.2020.20
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 7159
Ničković, D., Qin, X., Ferrere, T., Mateis, C., & Deshmukh, J. (2019). Shape expressions for specifying and extracting signal features. In 19th International Conference on Runtime Verification (Vol. 11757, pp. 292–309). Porto, Portugal: Springer Nature. https://doi.org/10.1007/978-3-030-32079-9_17
View | DOI
 
[12]
2019 | Conference Paper | IST-REx-ID: 7232
Ferrere, T., Maler, O., & Nickovic, D. (2019). Mixed-time signal temporal logic. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 11750, pp. 59–75). Amsterdam, The Netherlands: Springer Nature. https://doi.org/10.1007/978-3-030-29662-9_4
View | DOI
 
[11]
2019 | Journal Article | IST-REx-ID: 7109
Ferrere, T., Maler, O., Ničković, D., & Pnueli, A. (2019). From real-time logic to timed automata. Journal of the ACM, 66(3). https://doi.org/10.1145/3286976
View | DOI
 
[10]
2019 | Conference Paper | IST-REx-ID: 6428 | OA
Ferrere, T., Nickovic, D., Donzé, A., Ito, H., & Kapinski, J. (2019). Interface-aware signal temporal logic. In Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control (pp. 57–66). Montreal, Canada: ACM. https://doi.org/10.1145/3302504.3311800
View | Files available | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 78 | OA
Bakhirkin, A., Ferrere, T., Nickovic, D., Maler, O., & Asarin, E. (2018). Online timed pattern matching using automata (Vol. 11022, pp. 215–232). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Bejing, China: Springer. https://doi.org/10.1007/978-3-030-00151-3_13
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
Bakhirkin, A., Ferrere, T., Henzinger, T. A., & Nickovicl, D. (2018). Keynote: The first-order logic of signals. In 2018 International Conference on Embedded Software (pp. 1–10). Turin, Italy: IEEE. https://doi.org/10.1109/emsoft.2018.8537203
View | Files available | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 299 | OA
Nickovic, D., Lebeltel, O., Maler, O., Ferrere, T., & Ulus, D. (2018). AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. In D. Beyer & M. Huisman (Eds.) (Vol. 10806, pp. 303–319). Presented at the TACAS: Tools and Algorithms for the Construction and Analysis of Systems, Thessaloniki, Greece: Springer. https://doi.org/10.1007/978-3-319-89963-3_18
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 182 | OA
Bakhirkin, A., Ferrere, T., & Maler, O. (2018). Efficient parametric identification for STL. In Proceedings of the 21st International Conference on Hybrid Systems (pp. 177–186). Porto, Portugal: ACM. https://doi.org/10.1145/3178126.3178132
View | Files available | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 183
Bartocci, E., Ferrere, T., Manjunath, N., & Nickovic, D. (2018). Localizing faults in simulink/stateflow models with STL (pp. 197–206). Presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal: Association for Computing Machinery, Inc. https://doi.org/10.1145/3178126.3178131
View | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 144
Ferrere, T., Henzinger, T. A., & Saraç, E. (2018). A theory of register monitors (Vol. Part F138033, pp. 394–403). Presented at the LICS: Logic in Computer Science, Oxford, UK: IEEE. https://doi.org/10.1145/3209108.3209194
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 81 | OA
Elgyütt, A., Ferrere, T., & Henzinger, T. A. (2018). Monitoring temporal logic with clock variables (Vol. 11022, pp. 53–70). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China: Springer. https://doi.org/10.1007/978-3-030-00151-3_4
View | Files available | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 156 | OA
Ferrere, T. (2018). The compound interest in relaxing punctuality (Vol. 10951, pp. 147–164). Presented at the FM: International Symposium on Formal Methods, Oxford, UK: Springer. https://doi.org/10.1007/978-3-319-95582-7_9
View | Files available | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
Bakhirkin, A., Ferrere, T., Maler, O., & Ulus, D. (2017). On the quantitative semantics of regular expressions over real-valued signals. In A. Abate & G. Geeraerts (Eds.) (Vol. 10419, pp. 189–206). Presented at the FORMATS: Formal Modelling and Analysis of Timed Systems, Berlin, Germany: Springer. https://doi.org/10.1007/978-3-319-65765-3_11
View | DOI | Download Submitted Version (ext.)
 

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14 Publications

Mark all

[14]
2020 | Conference Paper | IST-REx-ID: 7348 | OA
Ferrere, T., Henzinger, T. A., & Kragl, B. (2020). Monitoring event frequencies. In 28th EACSL Annual Conference on Computer Science Logic (Vol. 152). Barcelona, Spain: Schloss Dagstuhl - Leibniz-Zentrum für Informatik. https://doi.org/10.4230/LIPIcs.CSL.2020.20
View | Files available | DOI | arXiv
 
[13]
2019 | Conference Paper | IST-REx-ID: 7159
Ničković, D., Qin, X., Ferrere, T., Mateis, C., & Deshmukh, J. (2019). Shape expressions for specifying and extracting signal features. In 19th International Conference on Runtime Verification (Vol. 11757, pp. 292–309). Porto, Portugal: Springer Nature. https://doi.org/10.1007/978-3-030-32079-9_17
View | DOI
 
[12]
2019 | Conference Paper | IST-REx-ID: 7232
Ferrere, T., Maler, O., & Nickovic, D. (2019). Mixed-time signal temporal logic. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 11750, pp. 59–75). Amsterdam, The Netherlands: Springer Nature. https://doi.org/10.1007/978-3-030-29662-9_4
View | DOI
 
[11]
2019 | Journal Article | IST-REx-ID: 7109
Ferrere, T., Maler, O., Ničković, D., & Pnueli, A. (2019). From real-time logic to timed automata. Journal of the ACM, 66(3). https://doi.org/10.1145/3286976
View | DOI
 
[10]
2019 | Conference Paper | IST-REx-ID: 6428 | OA
Ferrere, T., Nickovic, D., Donzé, A., Ito, H., & Kapinski, J. (2019). Interface-aware signal temporal logic. In Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control (pp. 57–66). Montreal, Canada: ACM. https://doi.org/10.1145/3302504.3311800
View | Files available | DOI
 
[9]
2018 | Conference Paper | IST-REx-ID: 78 | OA
Bakhirkin, A., Ferrere, T., Nickovic, D., Maler, O., & Asarin, E. (2018). Online timed pattern matching using automata (Vol. 11022, pp. 215–232). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Bejing, China: Springer. https://doi.org/10.1007/978-3-030-00151-3_13
View | Files available | DOI
 
[8]
2018 | Conference Paper | IST-REx-ID: 5959 | OA
Bakhirkin, A., Ferrere, T., Henzinger, T. A., & Nickovicl, D. (2018). Keynote: The first-order logic of signals. In 2018 International Conference on Embedded Software (pp. 1–10). Turin, Italy: IEEE. https://doi.org/10.1109/emsoft.2018.8537203
View | Files available | DOI
 
[7]
2018 | Conference Paper | IST-REx-ID: 299 | OA
Nickovic, D., Lebeltel, O., Maler, O., Ferrere, T., & Ulus, D. (2018). AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. In D. Beyer & M. Huisman (Eds.) (Vol. 10806, pp. 303–319). Presented at the TACAS: Tools and Algorithms for the Construction and Analysis of Systems, Thessaloniki, Greece: Springer. https://doi.org/10.1007/978-3-319-89963-3_18
View | Files available | DOI
 
[6]
2018 | Conference Paper | IST-REx-ID: 182 | OA
Bakhirkin, A., Ferrere, T., & Maler, O. (2018). Efficient parametric identification for STL. In Proceedings of the 21st International Conference on Hybrid Systems (pp. 177–186). Porto, Portugal: ACM. https://doi.org/10.1145/3178126.3178132
View | Files available | DOI
 
[5]
2018 | Conference Paper | IST-REx-ID: 183
Bartocci, E., Ferrere, T., Manjunath, N., & Nickovic, D. (2018). Localizing faults in simulink/stateflow models with STL (pp. 197–206). Presented at the HSCC: Hybrid Systems: Computation and Control, Porto, Portugal: Association for Computing Machinery, Inc. https://doi.org/10.1145/3178126.3178131
View | DOI
 
[4]
2018 | Conference Paper | IST-REx-ID: 144
Ferrere, T., Henzinger, T. A., & Saraç, E. (2018). A theory of register monitors (Vol. Part F138033, pp. 394–403). Presented at the LICS: Logic in Computer Science, Oxford, UK: IEEE. https://doi.org/10.1145/3209108.3209194
View | DOI
 
[3]
2018 | Conference Paper | IST-REx-ID: 81 | OA
Elgyütt, A., Ferrere, T., & Henzinger, T. A. (2018). Monitoring temporal logic with clock variables (Vol. 11022, pp. 53–70). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China: Springer. https://doi.org/10.1007/978-3-030-00151-3_4
View | Files available | DOI
 
[2]
2018 | Conference Paper | IST-REx-ID: 156 | OA
Ferrere, T. (2018). The compound interest in relaxing punctuality (Vol. 10951, pp. 147–164). Presented at the FM: International Symposium on Formal Methods, Oxford, UK: Springer. https://doi.org/10.1007/978-3-319-95582-7_9
View | Files available | DOI
 
[1]
2017 | Conference Paper | IST-REx-ID: 636 | OA
Bakhirkin, A., Ferrere, T., Maler, O., & Ulus, D. (2017). On the quantitative semantics of regular expressions over real-valued signals. In A. Abate & G. Geeraerts (Eds.) (Vol. 10419, pp. 189–206). Presented at the FORMATS: Formal Modelling and Analysis of Timed Systems, Berlin, Germany: Springer. https://doi.org/10.1007/978-3-319-65765-3_11
View | DOI | Download Submitted Version (ext.)
 

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