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2016 | Conference Paper | IST-REx-ID: 1256
Y. Jiang et al., “From stateflow simulation to verified implementation: A verification approach and a real-time train controller design,” presented at the RTAS: Real-time and Embedded Technology and Applications Symposium, Vienna, Austria, 2016.View | Files available | DOI
2016 | Conference Paper | IST-REx-ID: 1439
C. Dragoi, T. A. Henzinger, and D. Zufferey, “PSYNC: A partially synchronous language for fault-tolerant distributed algorithms,” presented at the POPL: Principles of Programming Languages, St. Petersburg, FL, USA, 2016, vol. 20–22, pp. 400–415.View | DOI | Download (ext.)