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386 Publications
2018 | Book Chapter | IST-REx-ID: 86 | 
Chatterjee K, Henzinger TA, Otop J. Computing average response time. In: Lohstroh M, Derler P, Sirjani M, eds. Principles of Modeling. Vol 10760. Springer; 2018:143-161. doi:10.1007/978-3-319-95246-8_9
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2018 | Conference Paper | IST-REx-ID: 6005 |
Avni G, Guha S, Kupferman O. Timed network games with clocks. In: Vol 117. Schloss Dagstuhl - Leibniz-Zentrum für Informatik; 2018. doi:10.4230/LIPICS.MFCS.2018.23
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2018 | Conference Paper | IST-REx-ID: 133 |
Kragl B, Qadeer S, Henzinger TA. Synchronizing the asynchronous. In: Vol 118. Schloss Dagstuhl - Leibniz-Zentrum für Informatik; 2018. doi:10.4230/LIPIcs.CONCUR.2018.21
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2018 | Conference Paper | IST-REx-ID: 299 |
Nickovic D, Lebeltel O, Maler O, Ferrere T, Ulus D. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. In: Beyer D, Huisman M, eds. Vol 10806. Springer; 2018:303-319. doi:10.1007/978-3-319-89963-3_18
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2018 | Conference Paper | IST-REx-ID: 144
Ferrere T, Henzinger TA, Saraç E. A theory of register monitors. In: Vol Part F138033. IEEE; 2018:394-403. doi:10.1145/3209108.3209194
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2018 | Conference Paper | IST-REx-ID: 182 |
Bakhirkin A, Ferrere T, Maler O. Efficient parametric identification for STL. In: Proceedings of the 21st International Conference on Hybrid Systems. ACM; 2018:177-186. doi:10.1145/3178126.3178132
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2018 | Conference Paper | IST-REx-ID: 5788 |
Avni G, Henzinger TA, Ibsen-Jensen R. Infinite-duration poorman-bidding games. In: Vol 11316. Springer; 2018:21-36. doi:10.1007/978-3-030-04612-5_2
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2018 | Conference Paper | IST-REx-ID: 160 |
Kragl B, Qadeer S. Layered Concurrent Programs. In: Vol 10981. Springer; 2018:79-102. doi:10.1007/978-3-319-96145-3_5
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2018 | Conference Paper | IST-REx-ID: 183
Bartocci E, Ferrere T, Manjunath N, Nickovic D. Localizing faults in simulink/stateflow models with STL. In: Association for Computing Machinery, Inc; 2018:197-206. doi:10.1145/3178126.3178131
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2018 | Conference Paper | IST-REx-ID: 81 |
Elgyütt A, Ferrere T, Henzinger TA. Monitoring temporal logic with clock variables. In: Vol 11022. Springer; 2018:53-70. doi:10.1007/978-3-030-00151-3_4
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