--- _id: '2298' abstract: - lang: eng text: "We present a shape analysis for programs that manipulate overlaid data structures which share sets of objects. The abstract domain contains Separation Logic formulas that (1) combine a per-object separating conjunction with a per-field separating conjunction and (2) constrain a set of variables interpreted as sets of objects. The definition of the abstract domain operators is based on a notion of homomorphism between formulas, viewed as graphs, used recently to define optimal decision procedures for fragments of the Separation Logic. Based on a Frame Rule that supports the two versions of the separating conjunction, the analysis is able to reason in a modular manner about non-overlaid data structures and then, compose information only at a few program points, e.g., procedure returns. We have implemented this analysis in a prototype tool and applied it on several interesting case studies that manipulate overlaid and nested linked lists.\r\n" alternative_title: - LNCS author: - first_name: Cezara full_name: Dragoi, Cezara id: 2B2B5ED0-F248-11E8-B48F-1D18A9856A87 last_name: Dragoi - first_name: Constantin full_name: Enea, Constantin last_name: Enea - first_name: Mihaela full_name: Sighireanu, Mihaela last_name: Sighireanu citation: ama: 'Dragoi C, Enea C, Sighireanu M. Local shape analysis for overlaid data structures. In: Vol 7935. Springer; 2013:150-171. doi:10.1007/978-3-642-38856-9_10' apa: 'Dragoi, C., Enea, C., & Sighireanu, M. (2013). Local shape analysis for overlaid data structures (Vol. 7935, pp. 150–171). Presented at the SAS: Static Analysis Symposium, Seattle, WA, United States: Springer. https://doi.org/10.1007/978-3-642-38856-9_10' chicago: Dragoi, Cezara, Constantin Enea, and Mihaela Sighireanu. “Local Shape Analysis for Overlaid Data Structures,” 7935:150–71. Springer, 2013. https://doi.org/10.1007/978-3-642-38856-9_10. ieee: 'C. Dragoi, C. Enea, and M. Sighireanu, “Local shape analysis for overlaid data structures,” presented at the SAS: Static Analysis Symposium, Seattle, WA, United States, 2013, vol. 7935, pp. 150–171.' ista: 'Dragoi C, Enea C, Sighireanu M. 2013. Local shape analysis for overlaid data structures. SAS: Static Analysis Symposium, LNCS, vol. 7935, 150–171.' mla: Dragoi, Cezara, et al. Local Shape Analysis for Overlaid Data Structures. Vol. 7935, Springer, 2013, pp. 150–71, doi:10.1007/978-3-642-38856-9_10. short: C. Dragoi, C. Enea, M. Sighireanu, in:, Springer, 2013, pp. 150–171. conference: end_date: 2013-06-22 location: Seattle, WA, United States name: 'SAS: Static Analysis Symposium' start_date: 2013-06-20 date_created: 2018-12-11T11:56:50Z date_published: 2013-01-01T00:00:00Z date_updated: 2021-01-12T06:56:36Z day: '01' ddc: - '000' - '004' department: - _id: ToHe doi: 10.1007/978-3-642-38856-9_10 ec_funded: 1 file: - access_level: open_access checksum: 907edd33a5892e3af093365f1fd57ed7 content_type: application/pdf creator: system date_created: 2018-12-12T10:10:36Z date_updated: 2020-07-14T12:45:37Z file_id: '4824' file_name: IST-2014-196-v1+1_sas13.pdf file_size: 299004 relation: main_file file_date_updated: 2020-07-14T12:45:37Z has_accepted_license: '1' intvolume: ' 7935' language: - iso: eng month: '01' oa: 1 oa_version: Submitted Version page: 150 - 171 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 25EE3708-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '267989' name: Quantitative Reactive Modeling publication_status: published publisher: Springer publist_id: '4630' pubrep_id: '196' quality_controlled: '1' scopus_import: 1 status: public title: Local shape analysis for overlaid data structures type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 7935 year: '2013' ... --- _id: '2299' abstract: - lang: eng text: 'The standard hardware design flow involves: (a) design of an integrated circuit using a hardware description language, (b) extensive functional and formal verification, and (c) logical synthesis. However, the above-mentioned processes consume significant effort and time. An alternative approach is to use a formal specification language as a high-level hardware description language and synthesize hardware from formal specifications. Our work is a case study of the synthesis of the widely and industrially used AMBA AHB protocol from formal specifications. Bloem et al. presented the first formal specifications for the AMBA AHB Arbiter and synthesized the AHB Arbiter circuit. However, in the first formal specification some important assumptions were missing. Our contributions are as follows: (a) We present detailed formal specifications for the AHB Arbiter incorporating the missing details, and obtain significant improvements in the synthesis results (both with respect to the number of gates in the synthesized circuit and with respect to the time taken to synthesize the circuit), and (b) we present formal specifications to generate compact circuits for the remaining two main components of AMBA AHB, namely, AHB Master and AHB Slave. Thus with systematic description we are able to automatically and completely synthesize an important and widely used industrial protocol.' author: - first_name: Yashdeep full_name: Godhal, Yashdeep id: 5B547124-EB61-11E9-8887-89D9C04DBDF5 last_name: Godhal - first_name: Krishnendu full_name: Chatterjee, Krishnendu id: 2E5DCA20-F248-11E8-B48F-1D18A9856A87 last_name: Chatterjee orcid: 0000-0002-4561-241X - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 citation: ama: 'Godhal Y, Chatterjee K, Henzinger TA. Synthesis of AMBA AHB from formal specification: A case study. International Journal on Software Tools for Technology Transfer. 2013;15(5-6):585-601. doi:10.1007/s10009-011-0207-9' apa: 'Godhal, Y., Chatterjee, K., & Henzinger, T. A. (2013). Synthesis of AMBA AHB from formal specification: A case study. International Journal on Software Tools for Technology Transfer. Springer. https://doi.org/10.1007/s10009-011-0207-9' chicago: 'Godhal, Yashdeep, Krishnendu Chatterjee, and Thomas A Henzinger. “Synthesis of AMBA AHB from Formal Specification: A Case Study.” International Journal on Software Tools for Technology Transfer. Springer, 2013. https://doi.org/10.1007/s10009-011-0207-9.' ieee: 'Y. Godhal, K. Chatterjee, and T. A. Henzinger, “Synthesis of AMBA AHB from formal specification: A case study,” International Journal on Software Tools for Technology Transfer, vol. 15, no. 5–6. Springer, pp. 585–601, 2013.' ista: 'Godhal Y, Chatterjee K, Henzinger TA. 2013. Synthesis of AMBA AHB from formal specification: A case study. International Journal on Software Tools for Technology Transfer. 15(5–6), 585–601.' mla: 'Godhal, Yashdeep, et al. “Synthesis of AMBA AHB from Formal Specification: A Case Study.” International Journal on Software Tools for Technology Transfer, vol. 15, no. 5–6, Springer, 2013, pp. 585–601, doi:10.1007/s10009-011-0207-9.' short: Y. Godhal, K. Chatterjee, T.A. Henzinger, International Journal on Software Tools for Technology Transfer 15 (2013) 585–601. date_created: 2018-12-11T11:56:51Z date_published: 2013-10-01T00:00:00Z date_updated: 2021-01-12T06:56:37Z day: '01' ddc: - '000' department: - _id: KrCh - _id: ToHe doi: 10.1007/s10009-011-0207-9 file: - access_level: open_access checksum: 57b06a732dd8d6349190dba6b5b0d33b content_type: application/pdf creator: system date_created: 2018-12-12T10:11:53Z date_updated: 2020-07-14T12:45:37Z file_id: '4910' file_name: IST-2012-87-v1+1_Synthesis_of_AMBA_AHB_from_formal_specifications-_A_case_study.pdf file_size: 277372 relation: main_file file_date_updated: 2020-07-14T12:45:37Z has_accepted_license: '1' intvolume: ' 15' issue: 5-6 language: - iso: eng month: '10' oa: 1 oa_version: Submitted Version page: 585 - 601 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 2587B514-B435-11E9-9278-68D0E5697425 name: Microsoft Research Faculty Fellowship publication: International Journal on Software Tools for Technology Transfer publication_status: published publisher: Springer publist_id: '4629' pubrep_id: '87' quality_controlled: '1' scopus_import: 1 status: public title: 'Synthesis of AMBA AHB from formal specification: A case study' type: journal_article user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 15 year: '2013' ... --- _id: '2301' abstract: - lang: eng text: We describe the design and implementation of P, a domain-specific language to write asynchronous event driven code. P allows the programmer to specify the system as a collection of interacting state machines, which communicate with each other using events. P unifies modeling and programming into one activity for the programmer. Not only can a P program be compiled into executable code, but it can also be tested using model checking techniques. P allows the programmer to specify the environment, used to "close" the system during testing, as nondeterministic ghost machines. Ghost machines are erased during compilation to executable code; a type system ensures that the erasure is semantics preserving. The P language is designed so that a P program can be checked for responsiveness-the ability to handle every event in a timely manner. By default, a machine needs to handle every event that arrives in every state. But handling every event in every state is impractical. The language provides a notion of deferred events where the programmer can annotate when she wants to delay processing an event. The default safety checker looks for presence of unhan-dled events. The language also provides default liveness checks that an event cannot be potentially deferred forever. P was used to implement and verify the core of the USB device driver stack that ships with Microsoft Windows 8. The resulting driver is more reliable and performs better than its prior incarnation (which did not use P); we have more confidence in the robustness of its design due to the language abstractions and verification provided by P. author: - first_name: Ankush full_name: Desai, Ankush last_name: Desai - first_name: Vivek full_name: Gupta, Vivek last_name: Gupta - first_name: Ethan full_name: Jackson, Ethan last_name: Jackson - first_name: Shaz full_name: Qadeer, Shaz last_name: Qadeer - first_name: Sriram full_name: Rajamani, Sriram last_name: Rajamani - first_name: Damien full_name: Zufferey, Damien id: 4397AC76-F248-11E8-B48F-1D18A9856A87 last_name: Zufferey orcid: 0000-0002-3197-8736 citation: ama: 'Desai A, Gupta V, Jackson E, Qadeer S, Rajamani S, Zufferey D. P: Safe asynchronous event-driven programming. In: Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation. ACM; 2013:321-331. doi:10.1145/2491956.2462184' apa: 'Desai, A., Gupta, V., Jackson, E., Qadeer, S., Rajamani, S., & Zufferey, D. (2013). P: Safe asynchronous event-driven programming. In Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation (pp. 321–331). Seattle, WA, United States: ACM. https://doi.org/10.1145/2491956.2462184' chicago: 'Desai, Ankush, Vivek Gupta, Ethan Jackson, Shaz Qadeer, Sriram Rajamani, and Damien Zufferey. “P: Safe Asynchronous Event-Driven Programming.” In Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, 321–31. ACM, 2013. https://doi.org/10.1145/2491956.2462184.' ieee: 'A. Desai, V. Gupta, E. Jackson, S. Qadeer, S. Rajamani, and D. Zufferey, “P: Safe asynchronous event-driven programming,” in Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, Seattle, WA, United States, 2013, pp. 321–331.' ista: 'Desai A, Gupta V, Jackson E, Qadeer S, Rajamani S, Zufferey D. 2013. P: Safe asynchronous event-driven programming. Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation. PLDI: Programming Languages Design and Implementation, 321–331.' mla: 'Desai, Ankush, et al. “P: Safe Asynchronous Event-Driven Programming.” Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, ACM, 2013, pp. 321–31, doi:10.1145/2491956.2462184.' short: A. Desai, V. Gupta, E. Jackson, S. Qadeer, S. Rajamani, D. Zufferey, in:, Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, ACM, 2013, pp. 321–331. conference: end_date: 2013-06-19 location: Seattle, WA, United States name: 'PLDI: Programming Languages Design and Implementation' start_date: 2013-06-16 date_created: 2018-12-11T11:56:52Z date_published: 2013-06-01T00:00:00Z date_updated: 2021-01-12T06:56:38Z day: '01' department: - _id: ToHe doi: 10.1145/2491956.2462184 ec_funded: 1 language: - iso: eng main_file_link: - url: http://research.microsoft.com/pubs/191069/pldi212_desai.pdf month: '06' oa_version: None page: 321 - 331 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 25EE3708-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '267989' name: Quantitative Reactive Modeling publication: Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation publication_status: published publisher: ACM publist_id: '4626' quality_controlled: '1' scopus_import: 1 status: public title: 'P: Safe asynchronous event-driven programming' type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 year: '2013' ... --- _id: '2328' abstract: - lang: eng text: "Linearizability of concurrent data structures is usually proved by monolithic simulation arguments relying on identifying the so-called linearization points. Regrettably, such proofs, whether manual or automatic, are often complicated and scale poorly to advanced non-blocking concurrency patterns, such as helping and optimistic updates.\r\nIn response, we propose a more modular way of checking linearizability of concurrent queue algorithms that does not involve identifying linearization points. We reduce the task of proving linearizability with respect to the queue specification to establishing four basic properties, each of which can be proved independently by simpler arguments. As a demonstration of our approach, we verify the Herlihy and Wing queue, an algorithm that is challenging to verify by a simulation proof." alternative_title: - LNCS author: - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 - first_name: Ali full_name: Sezgin, Ali id: 4C7638DA-F248-11E8-B48F-1D18A9856A87 last_name: Sezgin - first_name: Viktor full_name: Vafeiadis, Viktor last_name: Vafeiadis citation: ama: Henzinger TA, Sezgin A, Vafeiadis V. Aspect-oriented linearizability proofs. 2013;8052:242-256. doi:10.1007/978-3-642-40184-8_18 apa: 'Henzinger, T. A., Sezgin, A., & Vafeiadis, V. (2013). Aspect-oriented linearizability proofs. Presented at the CONCUR: Concurrency Theory, Buenos Aires, Argentina: Schloss Dagstuhl - Leibniz-Zentrum für Informatik. https://doi.org/10.1007/978-3-642-40184-8_18' chicago: Henzinger, Thomas A, Ali Sezgin, and Viktor Vafeiadis. “Aspect-Oriented Linearizability Proofs.” Lecture Notes in Computer Science. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2013. https://doi.org/10.1007/978-3-642-40184-8_18. ieee: T. A. Henzinger, A. Sezgin, and V. Vafeiadis, “Aspect-oriented linearizability proofs,” vol. 8052. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, pp. 242–256, 2013. ista: Henzinger TA, Sezgin A, Vafeiadis V. 2013. Aspect-oriented linearizability proofs. 8052, 242–256. mla: Henzinger, Thomas A., et al. Aspect-Oriented Linearizability Proofs. Vol. 8052, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2013, pp. 242–56, doi:10.1007/978-3-642-40184-8_18. short: T.A. Henzinger, A. Sezgin, V. Vafeiadis, 8052 (2013) 242–256. conference: end_date: 2013-08-30 location: Buenos Aires, Argentina name: 'CONCUR: Concurrency Theory' start_date: 2013-08-27 date_created: 2018-12-11T11:57:01Z date_published: 2013-08-01T00:00:00Z date_updated: 2023-02-23T10:16:27Z day: '01' ddc: - '000' - '004' department: - _id: ToHe doi: 10.1007/978-3-642-40184-8_18 ec_funded: 1 file: - access_level: open_access checksum: bdbb520de91751fe0136309ad4ef67e4 content_type: application/pdf creator: system date_created: 2018-12-12T10:08:58Z date_updated: 2020-07-14T12:45:39Z file_id: '4721' file_name: IST-2014-197-v1+1_main-queue-verification.pdf file_size: 337059 relation: main_file file_date_updated: 2020-07-14T12:45:39Z has_accepted_license: '1' intvolume: ' 8052' language: - iso: eng month: '08' oa: 1 oa_version: Submitted Version page: 242 - 256 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 25EE3708-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '267989' name: Quantitative Reactive Modeling publication_status: published publisher: Schloss Dagstuhl - Leibniz-Zentrum für Informatik publist_id: '4598' pubrep_id: '197' quality_controlled: '1' related_material: record: - id: '1832' relation: later_version status: public scopus_import: 1 series_title: Lecture Notes in Computer Science status: public title: Aspect-oriented linearizability proofs type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 8052 year: '2013' ... --- _id: '2447' abstract: - lang: eng text: "Separation logic (SL) has gained widespread popularity because of its ability to succinctly express complex invariants of a program’s heap configurations. Several specialized provers have been developed for decidable SL fragments. However, these provers cannot be easily extended or combined with solvers for other theories that are important in program verification, e.g., linear arithmetic. In this paper, we present a reduction of decidable SL fragments to a decidable first-order theory that fits well into the satisfiability modulo theories (SMT) framework. We show how to use this reduction to automate satisfiability, entailment, frame inference, and abduction problems for separation logic using SMT solvers. Our approach provides a simple method of integrating separation logic into existing verification tools that provide SMT backends, and an elegant way of combining SL fragments with other decidable first-order theories. We implemented this approach in a verification tool and applied it to heap-manipulating programs whose verification involves reasoning in theory combinations.\r\n" alternative_title: - LNCS article_processing_charge: No author: - first_name: Ruzica full_name: Piskac, Ruzica last_name: Piskac - first_name: Thomas full_name: Wies, Thomas id: 447BFB88-F248-11E8-B48F-1D18A9856A87 last_name: Wies - first_name: Damien full_name: Zufferey, Damien id: 4397AC76-F248-11E8-B48F-1D18A9856A87 last_name: Zufferey orcid: 0000-0002-3197-8736 citation: ama: Piskac R, Wies T, Zufferey D. Automating separation logic using SMT. 2013;8044:773-789. doi:10.1007/978-3-642-39799-8_54 apa: 'Piskac, R., Wies, T., & Zufferey, D. (2013). Automating separation logic using SMT. Presented at the CAV: Computer Aided Verification, St. Petersburg, Russia: Springer. https://doi.org/10.1007/978-3-642-39799-8_54' chicago: Piskac, Ruzica, Thomas Wies, and Damien Zufferey. “Automating Separation Logic Using SMT.” Lecture Notes in Computer Science. Springer, 2013. https://doi.org/10.1007/978-3-642-39799-8_54. ieee: R. Piskac, T. Wies, and D. Zufferey, “Automating separation logic using SMT,” vol. 8044. Springer, pp. 773–789, 2013. ista: Piskac R, Wies T, Zufferey D. 2013. Automating separation logic using SMT. 8044, 773–789. mla: Piskac, Ruzica, et al. Automating Separation Logic Using SMT. Vol. 8044, Springer, 2013, pp. 773–89, doi:10.1007/978-3-642-39799-8_54. short: R. Piskac, T. Wies, D. Zufferey, 8044 (2013) 773–789. conference: end_date: 2013-07-19 location: St. Petersburg, Russia name: 'CAV: Computer Aided Verification' start_date: 2013-07-13 date_created: 2018-12-11T11:57:43Z date_published: 2013-07-01T00:00:00Z date_updated: 2020-08-11T10:09:47Z day: '01' ddc: - '000' department: - _id: ToHe doi: 10.1007/978-3-642-39799-8_54 file: - access_level: open_access checksum: 2e866932ab688f47ecd504acb4d5c7d4 content_type: application/pdf creator: dernst date_created: 2020-05-15T11:13:01Z date_updated: 2020-07-14T12:45:41Z file_id: '7859' file_name: 2013_CAV_Piskac.pdf file_size: 309182 relation: main_file file_date_updated: 2020-07-14T12:45:41Z has_accepted_license: '1' intvolume: ' 8044' language: - iso: eng month: '07' oa: 1 oa_version: Submitted Version page: 773 - 789 publication_status: published publisher: Springer publist_id: '4456' quality_controlled: '1' scopus_import: 1 series_title: Lecture Notes in Computer Science status: public title: Automating separation logic using SMT type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 8044 year: '2013' ... --- _id: '2517' abstract: - lang: eng text: 'Traditional formal methods are based on a Boolean satisfaction notion: a reactive system satisfies, or not, a given specification. We generalize formal methods to also address the quality of systems. As an adequate specification formalism we introduce the linear temporal logic LTL[F]. The satisfaction value of an LTL[F] formula is a number between 0 and 1, describing the quality of the satisfaction. The logic generalizes traditional LTL by augmenting it with a (parameterized) set F of arbitrary functions over the interval [0,1]. For example, F may contain the maximum or minimum between the satisfaction values of subformulas, their product, and their average. The classical decision problems in formal methods, such as satisfiability, model checking, and synthesis, are generalized to search and optimization problems in the quantitative setting. For example, model checking asks for the quality in which a specification is satisfied, and synthesis returns a system satisfying the specification with the highest quality. Reasoning about quality gives rise to other natural questions, like the distance between specifications. We formalize these basic questions and study them for LTL[F]. By extending the automata-theoretic approach for LTL to a setting that takes quality into an account, we are able to solve the above problems and show that reasoning about LTL[F] has roughly the same complexity as reasoning about traditional LTL.' acknowledgement: 'ERC Grant QUALITY. ' alternative_title: - LNCS article_processing_charge: No author: - first_name: Shaull full_name: Almagor, Shaull last_name: Almagor - first_name: Udi full_name: Boker, Udi id: 31E297B6-F248-11E8-B48F-1D18A9856A87 last_name: Boker - first_name: Orna full_name: Kupferman, Orna last_name: Kupferman citation: ama: Almagor S, Boker U, Kupferman O. Formalizing and reasoning about quality. 2013;7966(Part 2):15-27. doi:10.1007/978-3-642-39212-2_3 apa: 'Almagor, S., Boker, U., & Kupferman, O. (2013). Formalizing and reasoning about quality. Presented at the ICALP: Automata, Languages and Programming, Riga, Latvia: Springer. https://doi.org/10.1007/978-3-642-39212-2_3' chicago: Almagor, Shaull, Udi Boker, and Orna Kupferman. “Formalizing and Reasoning about Quality.” Lecture Notes in Computer Science. Springer, 2013. https://doi.org/10.1007/978-3-642-39212-2_3. ieee: S. Almagor, U. Boker, and O. Kupferman, “Formalizing and reasoning about quality,” vol. 7966, no. Part 2. Springer, pp. 15–27, 2013. ista: Almagor S, Boker U, Kupferman O. 2013. Formalizing and reasoning about quality. 7966(Part 2), 15–27. mla: Almagor, Shaull, et al. Formalizing and Reasoning about Quality. Vol. 7966, no. Part 2, Springer, 2013, pp. 15–27, doi:10.1007/978-3-642-39212-2_3. short: S. Almagor, U. Boker, O. Kupferman, 7966 (2013) 15–27. conference: end_date: 2013-07-12 location: Riga, Latvia name: 'ICALP: Automata, Languages and Programming' start_date: 2013-07-08 date_created: 2018-12-11T11:58:08Z date_published: 2013-07-01T00:00:00Z date_updated: 2020-08-11T10:09:47Z day: '01' ddc: - '000' department: - _id: ToHe doi: 10.1007/978-3-642-39212-2_3 ec_funded: 1 file: - access_level: open_access checksum: 85afbf6c18a2c7e377c52c9410e2d824 content_type: application/pdf creator: dernst date_created: 2020-05-15T11:16:12Z date_updated: 2020-07-14T12:45:42Z file_id: '7860' file_name: 2013_ICALP_Almagor.pdf file_size: 363031 relation: main_file file_date_updated: 2020-07-14T12:45:42Z has_accepted_license: '1' intvolume: ' 7966' issue: Part 2 language: - iso: eng month: '07' oa: 1 oa_version: Submitted Version page: 15 - 27 project: - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 25EE3708-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '267989' name: Quantitative Reactive Modeling publication_status: published publisher: Springer publist_id: '4384' quality_controlled: '1' scopus_import: 1 series_title: Lecture Notes in Computer Science status: public title: Formalizing and reasoning about quality type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 7966 year: '2013' ... --- _id: '2854' abstract: - lang: eng text: We consider concurrent games played on graphs. At every round of a game, each player simultaneously and independently selects a move; the moves jointly determine the transition to a successor state. Two basic objectives are the safety objective to stay forever in a given set of states, and its dual, the reachability objective to reach a given set of states. First, we present a simple proof of the fact that in concurrent reachability games, for all ε>0, memoryless ε-optimal strategies exist. A memoryless strategy is independent of the history of plays, and an ε-optimal strategy achieves the objective with probability within ε of the value of the game. In contrast to previous proofs of this fact, our proof is more elementary and more combinatorial. Second, we present a strategy-improvement (a.k.a. policy-iteration) algorithm for concurrent games with reachability objectives. Finally, we present a strategy-improvement algorithm for turn-based stochastic games (where each player selects moves in turns) with safety objectives. Our algorithms yield sequences of player-1 strategies which ensure probabilities of winning that converge monotonically (from below) to the value of the game. © 2012 Elsevier Inc. acknowledgement: This work was partially supported in part by the NSF grants CCR-0132780, CNS-0720884, CCR-0225610, by the Swiss National Science Foundation, ERC Start Grant Graph Games (Project No. 279307), FWF NFN Grant S11407-N23 (RiSE), and a Microsoft faculty fellows article_processing_charge: No article_type: original author: - first_name: Krishnendu full_name: Chatterjee, Krishnendu id: 2E5DCA20-F248-11E8-B48F-1D18A9856A87 last_name: Chatterjee orcid: 0000-0002-4561-241X - first_name: Luca full_name: De Alfaro, Luca last_name: De Alfaro - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 citation: ama: Chatterjee K, De Alfaro L, Henzinger TA. Strategy improvement for concurrent reachability and turn based stochastic safety games. Journal of Computer and System Sciences. 2013;79(5):640-657. doi:10.1016/j.jcss.2012.12.001 apa: Chatterjee, K., De Alfaro, L., & Henzinger, T. A. (2013). Strategy improvement for concurrent reachability and turn based stochastic safety games. Journal of Computer and System Sciences. Elsevier. https://doi.org/10.1016/j.jcss.2012.12.001 chicago: Chatterjee, Krishnendu, Luca De Alfaro, and Thomas A Henzinger. “Strategy Improvement for Concurrent Reachability and Turn Based Stochastic Safety Games.” Journal of Computer and System Sciences. Elsevier, 2013. https://doi.org/10.1016/j.jcss.2012.12.001. ieee: K. Chatterjee, L. De Alfaro, and T. A. Henzinger, “Strategy improvement for concurrent reachability and turn based stochastic safety games,” Journal of Computer and System Sciences, vol. 79, no. 5. Elsevier, pp. 640–657, 2013. ista: Chatterjee K, De Alfaro L, Henzinger TA. 2013. Strategy improvement for concurrent reachability and turn based stochastic safety games. Journal of Computer and System Sciences. 79(5), 640–657. mla: Chatterjee, Krishnendu, et al. “Strategy Improvement for Concurrent Reachability and Turn Based Stochastic Safety Games.” Journal of Computer and System Sciences, vol. 79, no. 5, Elsevier, 2013, pp. 640–57, doi:10.1016/j.jcss.2012.12.001. short: K. Chatterjee, L. De Alfaro, T.A. Henzinger, Journal of Computer and System Sciences 79 (2013) 640–657. date_created: 2018-12-11T11:59:57Z date_published: 2013-08-01T00:00:00Z date_updated: 2021-01-12T07:00:16Z day: '01' ddc: - '000' department: - _id: KrCh - _id: ToHe doi: 10.1016/j.jcss.2012.12.001 ec_funded: 1 file: - access_level: open_access checksum: 6d3ee12cceb946a0abe69594b6a22409 content_type: application/pdf creator: system date_created: 2018-12-12T10:18:48Z date_updated: 2020-07-14T12:45:51Z file_id: '5370' file_name: IST-2015-388-v1+1_1-s2.0-S0022000012001778-main.pdf file_size: 425488 relation: main_file file_date_updated: 2020-07-14T12:45:51Z has_accepted_license: '1' intvolume: ' 79' issue: '5' language: - iso: eng license: https://creativecommons.org/licenses/by-nc-nd/4.0/ month: '08' oa: 1 oa_version: Published Version page: 640 - 657 project: - _id: 2581B60A-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '279307' name: 'Quantitative Graph Games: Theory and Applications' - _id: 25863FF4-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S11407 name: Game Theory - _id: 2587B514-B435-11E9-9278-68D0E5697425 name: Microsoft Research Faculty Fellowship publication: Journal of Computer and System Sciences publication_status: published publisher: Elsevier publist_id: '3938' pubrep_id: '388' quality_controlled: '1' scopus_import: 1 status: public title: Strategy improvement for concurrent reachability and turn based stochastic safety games tmp: image: /images/cc_by_nc_nd.png legal_code_url: https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode name: Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) short: CC BY-NC-ND (4.0) type: journal_article user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 79 year: '2013' ... --- _id: '2885' abstract: - lang: eng text: 'This volume contains the post-proceedings of the 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, MEMICS 2012, held in Znojmo, Czech Republic, in October, 2012. The 13 thoroughly revised papers were carefully selected out of 31 submissions and are presented together with 6 invited papers. The topics covered by the papers include: computer-aided analysis and verification, applications of game theory in computer science, networks and security, modern trends of graph theory in computer science, electronic systems design and testing, and quantum information processing.' acknowledgement: Red Hat Czech Republic, Y Soft alternative_title: - LNCS citation: ama: Kucera A, Henzinger TA, Nesetril J, Vojnar T, Antos D, eds. Mathematical and Engineering Methods in Computer Science. Vol 7721. Springer; 2013:1-228. doi:10.1007/978-3-642-36046-6 apa: 'Kucera, A., Henzinger, T. A., Nesetril, J., Vojnar, T., & Antos, D. (Eds.). (2013). Mathematical and Engineering Methods in Computer Science (Vol. 7721, pp. 1–228). Presented at the MEMICS: Mathematical and Engineering methods in computer science, Znojmo, Czech Republic: Springer. https://doi.org/10.1007/978-3-642-36046-6' chicago: Kucera, Antonin, Thomas A Henzinger, Jaroslav Nesetril, Tomas Vojnar, and David Antos, eds. Mathematical and Engineering Methods in Computer Science. Vol. 7721. Lecture Notes in Computer Science. Springer, 2013. https://doi.org/10.1007/978-3-642-36046-6. ieee: A. Kucera, T. A. Henzinger, J. Nesetril, T. Vojnar, and D. Antos, Eds., Mathematical and Engineering Methods in Computer Science, vol. 7721. Springer, 2013, pp. 1–228. ista: Kucera A, Henzinger TA, Nesetril J, Vojnar T, Antos D eds. 2013. Mathematical and Engineering Methods in Computer Science, Springer,p. mla: Kucera, Antonin, et al., editors. Mathematical and Engineering Methods in Computer Science. Vol. 7721, Springer, 2013, pp. 1–228, doi:10.1007/978-3-642-36046-6. short: A. Kucera, T.A. Henzinger, J. Nesetril, T. Vojnar, D. Antos, eds., Mathematical and Engineering Methods in Computer Science, Springer, 2013. conference: end_date: 2012-10-28 location: Znojmo, Czech Republic name: 'MEMICS: Mathematical and Engineering methods in computer science' start_date: 2012-10-25 date_created: 2018-12-11T12:00:08Z date_published: 2013-01-09T00:00:00Z date_updated: 2019-08-02T12:37:55Z day: '09' department: - _id: ToHe doi: 10.1007/978-3-642-36046-6 editor: - first_name: Antonin full_name: Kucera, Antonin last_name: Kucera - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 - first_name: Jaroslav full_name: Nesetril, Jaroslav last_name: Nesetril - first_name: Tomas full_name: Vojnar, Tomas last_name: Vojnar - first_name: David full_name: Antos, David last_name: Antos intvolume: ' 7721' language: - iso: eng month: '01' oa_version: None page: 1 - 228 publication_status: published publisher: Springer publist_id: '3874' quality_controlled: '1' series_title: Lecture Notes in Computer Science status: public title: Mathematical and Engineering Methods in Computer Science type: conference_editor user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 volume: 7721 year: '2013' ... --- _id: '5402' abstract: - lang: eng text: "Linearizability requires that the outcome of calls by competing threads to a concurrent data structure is the same as some sequential execution where each thread has exclusive access to the data structure. In an ordered data structure, such as a queue or a stack, linearizability is ensured by requiring threads commit in the order dictated by the sequential semantics of the data structure; e.g., in a concurrent queue implementation a dequeue can only remove the oldest element. \r\nIn this paper, we investigate the impact of this strict ordering, by comparing what linearizability allows to what existing implementations do. We first give an operational definition for linearizability which allows us to build the most general linearizable implementation as a transition system for any given sequential specification. We then use this operational definition to categorize linearizable implementations based on whether they are bound or free. In a bound implementation, whenever all threads observe the same logical state, the updates to the logical state and the temporal order of commits coincide. All existing queue implementations we know of are bound. We then proceed to present, to the best of our knowledge, the first ever free queue implementation. Our experiments show that free implementations have the potential for better performance by suffering less from contention." alternative_title: - IST Austria Technical Report author: - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 - first_name: Ali full_name: Sezgin, Ali id: 4C7638DA-F248-11E8-B48F-1D18A9856A87 last_name: Sezgin citation: ama: Henzinger TA, Sezgin A. How Free Is Your Linearizable Concurrent Data Structure? IST Austria; 2013. doi:10.15479/AT:IST-2013-123-v1-1 apa: Henzinger, T. A., & Sezgin, A. (2013). How free is your linearizable concurrent data structure? IST Austria. https://doi.org/10.15479/AT:IST-2013-123-v1-1 chicago: Henzinger, Thomas A, and Ali Sezgin. How Free Is Your Linearizable Concurrent Data Structure? IST Austria, 2013. https://doi.org/10.15479/AT:IST-2013-123-v1-1. ieee: T. A. Henzinger and A. Sezgin, How free is your linearizable concurrent data structure? IST Austria, 2013. ista: Henzinger TA, Sezgin A. 2013. How free is your linearizable concurrent data structure?, IST Austria, 16p. mla: Henzinger, Thomas A., and Ali Sezgin. How Free Is Your Linearizable Concurrent Data Structure? IST Austria, 2013, doi:10.15479/AT:IST-2013-123-v1-1. short: T.A. Henzinger, A. Sezgin, How Free Is Your Linearizable Concurrent Data Structure?, IST Austria, 2013. date_created: 2018-12-12T11:39:07Z date_published: 2013-06-12T00:00:00Z date_updated: 2020-07-14T23:04:47Z day: '12' ddc: - '000' - '004' department: - _id: ToHe doi: 10.15479/AT:IST-2013-123-v1-1 file: - access_level: open_access checksum: ce580605ae9756a8c99d7b403ebb8eed content_type: application/pdf creator: system date_created: 2018-12-12T11:53:19Z date_updated: 2020-07-14T12:46:45Z file_id: '5480' file_name: IST-2013-123-v1+1_main-concur2013.pdf file_size: 249790 relation: main_file file_date_updated: 2020-07-14T12:46:45Z has_accepted_license: '1' language: - iso: eng month: '06' oa: 1 oa_version: Published Version page: '16' publication_identifier: issn: - 2664-1690 publication_status: published publisher: IST Austria pubrep_id: '123' status: public title: How free is your linearizable concurrent data structure? type: technical_report user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 year: '2013' ... --- _id: '1376' abstract: - lang: eng text: 'We consider the distributed synthesis problem for temporal logic specifications. Traditionally, the problem has been studied for LTL, and the previous results show that the problem is decidable iff there is no information fork in the architecture. We consider the problem for fragments of LTL and our main results are as follows: (1) We show that the problem is undecidable for architectures with information forks even for the fragment of LTL with temporal operators restricted to next and eventually. (2) For specifications restricted to globally along with non-nested next operators, we establish decidability (in EXPSPACE) for star architectures where the processes receive disjoint inputs, whereas we establish undecidability for architectures containing an information fork-meet structure. (3) Finally, we consider LTL without the next operator, and establish decidability (NEXPTIME-complete) for all architectures for a fragment that consists of a set of safety assumptions, and a set of guarantees where each guarantee is a safety, reachability, or liveness condition.' author: - first_name: Krishnendu full_name: Chatterjee, Krishnendu id: 2E5DCA20-F248-11E8-B48F-1D18A9856A87 last_name: Chatterjee orcid: 0000-0002-4561-241X - first_name: Thomas A full_name: Henzinger, Thomas A id: 40876CD8-F248-11E8-B48F-1D18A9856A87 last_name: Henzinger orcid: 0000−0002−2985−7724 - first_name: Jan full_name: Otop, Jan id: 2FC5DA74-F248-11E8-B48F-1D18A9856A87 last_name: Otop - first_name: Andreas full_name: Pavlogiannis, Andreas id: 49704004-F248-11E8-B48F-1D18A9856A87 last_name: Pavlogiannis orcid: 0000-0002-8943-0722 citation: ama: 'Chatterjee K, Henzinger TA, Otop J, Pavlogiannis A. Distributed synthesis for LTL fragments. In: 13th International Conference on Formal Methods in Computer-Aided Design. IEEE; 2013:18-25. doi:10.1109/FMCAD.2013.6679386' apa: 'Chatterjee, K., Henzinger, T. A., Otop, J., & Pavlogiannis, A. (2013). Distributed synthesis for LTL fragments. In 13th International Conference on Formal Methods in Computer-Aided Design (pp. 18–25). Portland, OR, United States: IEEE. https://doi.org/10.1109/FMCAD.2013.6679386' chicago: Chatterjee, Krishnendu, Thomas A Henzinger, Jan Otop, and Andreas Pavlogiannis. “Distributed Synthesis for LTL Fragments.” In 13th International Conference on Formal Methods in Computer-Aided Design, 18–25. IEEE, 2013. https://doi.org/10.1109/FMCAD.2013.6679386. ieee: K. Chatterjee, T. A. Henzinger, J. Otop, and A. Pavlogiannis, “Distributed synthesis for LTL fragments,” in 13th International Conference on Formal Methods in Computer-Aided Design, Portland, OR, United States, 2013, pp. 18–25. ista: 'Chatterjee K, Henzinger TA, Otop J, Pavlogiannis A. 2013. Distributed synthesis for LTL fragments. 13th International Conference on Formal Methods in Computer-Aided Design. FMCAD: Formal Methods in Computer-Aided Design, 18–25.' mla: Chatterjee, Krishnendu, et al. “Distributed Synthesis for LTL Fragments.” 13th International Conference on Formal Methods in Computer-Aided Design, IEEE, 2013, pp. 18–25, doi:10.1109/FMCAD.2013.6679386. short: K. Chatterjee, T.A. Henzinger, J. Otop, A. Pavlogiannis, in:, 13th International Conference on Formal Methods in Computer-Aided Design, IEEE, 2013, pp. 18–25. conference: end_date: 2013-10-23 location: Portland, OR, United States name: 'FMCAD: Formal Methods in Computer-Aided Design' start_date: 2013-10-20 date_created: 2018-12-11T11:51:40Z date_published: 2013-12-11T00:00:00Z date_updated: 2023-02-23T12:24:53Z day: '11' department: - _id: KrCh - _id: ToHe doi: 10.1109/FMCAD.2013.6679386 ec_funded: 1 language: - iso: eng month: '12' oa_version: None page: 18 - 25 project: - _id: 2584A770-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: P 23499-N23 name: Modern Graph Algorithmic Techniques in Formal Verification - _id: 25832EC2-B435-11E9-9278-68D0E5697425 call_identifier: FWF grant_number: S 11407_N23 name: Rigorous Systems Engineering - _id: 2581B60A-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '279307' name: 'Quantitative Graph Games: Theory and Applications' - _id: 25EE3708-B435-11E9-9278-68D0E5697425 call_identifier: FP7 grant_number: '267989' name: Quantitative Reactive Modeling - _id: 2587B514-B435-11E9-9278-68D0E5697425 name: Microsoft Research Faculty Fellowship publication: 13th International Conference on Formal Methods in Computer-Aided Design publication_status: published publisher: IEEE publist_id: '5835' quality_controlled: '1' related_material: record: - id: '5406' relation: earlier_version status: public status: public title: Distributed synthesis for LTL fragments type: conference user_id: 2DF688A6-F248-11E8-B48F-1D18A9856A87 year: '2013' ...